The present invention relates generally to the electrical, electronic and computer arts and, more particularly, to vertical transistor structures.
Metal oxide semiconductor field-effect transistors (MOSFETs) include gate electrodes that are electrically insulated from operatively associated semiconductor channels by thin layers of dielectric material. MOSFETs having n-doped source and drain regions employ electrons as the primary current carriers while those having p-doped source and drain regions use holes as primary current carriers. Vertical field-effect transistors (VFETs) have configurations wherein the current between the drain and source regions is substantially normal to the surface of the die. A vertical field-effect transistor may, for example, include a semiconductor pillar or fin having top and bottom regions comprising source/drain regions, the portion of the pillar between the source/drain regions defining a channel region. Vertical field-effect transistors (VFETs) are characterized by doped, possibly vertical channel regions, p-n junctions on one or more sides of the channels, and ohmic contacts forming the source and drain regions.
Vertical FETs (VFETs) are a promising alternative to standard lateral FET structures due to potential benefits, among others, in terms of reduced circuit footprint. VFETs can potentially provide electronic devices comprising logic circuits with improved circuit density. Such logic circuits can be characterized by a lower-number CPP (cell gate pitch) versus comparable logic circuits comprising lateral FET layouts. Minimum wiring pitch can also be relevant for realizing denser vertical FET layouts.
Sidewall image transfer (SIT) is a widely used technique for tight semiconductor fin patterning, for example arrays of silicon fins with a pitch of 18-28 nm. Optical lithography (OPL) patterning can result in “fin pitch walking.” Pitch walking refers to the presence of different periodicities in an array due to the lithographic process employed in forming the array. Fin pitch walking and iso-dense bias may lead to variable metal gate recess depth which may in turn lead to variable gate length and variable device performance.